EP2S30F484C3N FPGA - Field Programmable Gate Array FPGA - Stratix II 1694 LABs 342 IOs

                                                    EP2S30F484C3N Datasheet

Product Details

[Altera]

Introduction

The Stratix® II FPGA family is based on a 1.2-V, 90-nm, all-layer copper SRAM process and features a new logic structure that maximizes performance, and enables device densities approaching 180,000 equivalent logic elements (LEs). Stratix II devices offer up to 9 Mbits of on-chip, TriMatrix™ memory for demanding, memory intensive applications and has up to 96 DSP blocks with up to 384 (18-bit × 18-bit) multipliers for efficient implementation of high performance filters and other DSP functions.

Features

The Stratix II family offers the following features:
■ 15,600 to 179,400 equivalent LEs; see Table 1–1
■ New and innovative adaptive logic module (ALM), the basic building block of the Stratix II architecture, maximizes performance and resource usage efficiency
■ Up to 9,383,040 RAM bits (1,172,880 bytes) available without reducing logic resources
■ TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers
■ High-speed DSP blocks provide dedicated implementation of multipliers (at up to 450 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters
■ Up to 16 global clocks with 24 clocking resources per device region
■ Clock control blocks support dynamic clock network enable/disable, which allows clock networks to power down to reduce power consumption in user mode
■ Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting
■ Support for numerous single-ended and differential I/O standards
■ High-speed differential I/O support with DPA circuitry for 1-Gbps performance
■ Support for high-speed networking and communications bus standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY Level 4), HyperTransport™ technology, and SFI-4
■ Support for high-speed external memory, including DDR and DDR2 SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM
■ Support for multiple intellectual property megafunctions from Altera MegaCore® functions and Altera Megafunction Partners Program (AMPPSM) megafunctions
■ Support for design security using configuration bitstream encryption
■ Support for remote configuration updates

Specifications

Form,Package,Functional compatible component

Descriptions

Who we are?

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FAQ
Q: Are you trading company or manufacturer?
A: We are original manufacturer OF Integrated Circuit Chip . We can do OEM/ODM business.
Q: How long is your delivery time?
A: Group buying delivery time: 30-60 days; General delivery time: 20 days.
Q: What is your terms of payment?
A: T/T 30% as deposit, and 70% before delivery.
Q: How to buy your products?
A: You can buy the products from our company directly.Normally the procedure is sign the contract, payment by T/T,Contact the shipping company to delivery the goods to your country.Q: What is the warranty ?
A: The free warranty is one year from the day of Commissioning qualified.If there is any fault for our products within the free warranty period, we will repair it and change the fault assembly for free