FS32K144HAT0MLHT ARM Microcontrollers - MCU S32K144 Arm Cortex-M4F 80MHz 512Kb Flash CAN FD FlexIO CSEc security LQFP64

                                                                  FS32K144HAT0MLHT Datasheet

Product Details

Description

Supports S32K116, S32K118, S32K142, S32K142W, S32K144, S32K144W, S32K146, and S32K148 – Technical information for S32K142W and S32K144W device families is preliminary until these devices achieve qualification

Features

• Operating characteristics
– Voltage range: 2.7 V to 5.5 V
– Ambient temperature range: -40 °C to 105 °C for HSRUN mode, -40 °C to 150 °C for RUN mode
• Arm™ Cortex-M4F/M0+ core, 32-bit CPU
– Supports up to 112 MHz frequency (HSRUN mode) with 1.25 Dhrystone MIPS per MHz
– Arm Core based on the Armv7 Architecture and Thumb®-2 ISA
– Integrated Digital Signal Processor (DSP)
– Configurable Nested Vectored Interrupt Controller (NVIC)
– Single Precision Floating Point Unit (FPU)
• Clock interfaces
– 4 - 40 MHz fast external oscillator (SOSC) with up to 50 MHz DC external square input clock in external clock mode
– 48 MHz Fast Internal RC oscillator (FIRC)
– 8 MHz Slow Internal RC oscillator (SIRC)
– 128 kHz Low Power Oscillator (LPO)
– Up to 112 MHz (HSRUN) System Phased Lock Loop (SPLL)
– Up to 20 MHz TCLK and 25 MHz SWD_CLK
– 32 kHz Real Time Counter external clock (RTC_CLKIN)

• Power management
– Low-power Arm Cortex-M4F/M0+ core with excellent energy efficiency
– Power Management Controller (PMC) with multiple power modes: HSRUN, RUN, STOP, VLPR, and VLPS. Note: CSEc (Security) or EEPROM writes/ erase will trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. The device will need to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase.
– Clock gating and low power operation supported on specific peripherals.
• Memory and memory interfaces
– Up to 2 MB program flash memory with ECC
– 64 KB FlexNVM for data flash memory with ECC and EEPROM emulation. Note: CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. The device will need to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase.
– Up to 256 KB SRAM with ECC
– Up to 4 KB of FlexRAM for use as SRAM or EEPROM emulation
– Up to 4 KB Code cache to minimize performance impact of memory access latencies
– QuadSPI with HyperBus™ support
• Mixed-signal analog
– Up to two 12-bit Analog-to-Digital Converter (ADC) with up to 32 channel analog inputs per module
– One Analog Comparator (CMP) with internal 8-bit Digital to Analog Converter (DAC)
• Debug functionality
– Serial Wire JTAG Debug Port (SWJ-DP) combines
– Debug Watchpoint and Trace (DWT)
– Instrumentation Trace Macrocell (ITM)
– Test Port Interface Unit (TPIU)
– Flash Patch and Breakpoint (FPB) Unit
• Human-machine interface (HMI)
– Up to 156 GPIO pins with interrupt functionality

Specifications

Who we are?