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EP1SGX25FF1020I6N FPGA - Field Programmable Gate Array FPGA - Stratix I GX 2566 LABs 607 IOs
  • EP1SGX25FF1020I6N FPGA - Field Programmable Gate Array FPGA - Stratix I GX 2566 LABs 607 IOs

EP1SGX25FF1020I6N FPGA - Field Programmable Gate Array FPGA - Stratix I GX 2566 LABs 607 IOs

Place of Origin Call
Brand Name Intel / Altera
Certification ROHS
Model Number EP1SGX25FF1020I6N
Product Details
Product Name:
EP1SGX25FF1020I6N
Condition:
Original 100%
Installation Methodpe:
FPGA 607 I/O Surface Mount 607 I/O -40°C ~ 100°C (TJ) 1020-BBGA, FCBGA Stratix® GX 1944576 Bits 1.425 V ~ 1.575 V
Package:
1020-BBGA, FCBGA
Voltage - Supply:
International Standard
Max. Reverse Current:
International Standard
Application:
FPGAs (Field Programmable Gate Array)
Product Description

                                                         EP1SGX25FF1020I6N FPGA - Field Programmable Gate Array FPGA - Stratix I GX 2566 LABs 607 IOs 0EP1SGX25FF1020I6N Datasheet

Product Details

This datasheet describes configuration devices for SRAM-based look-up table (LUT) devices.

Features

Configuration devices for SRAM-based LUT devices offer the following features:
■ Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices
■ Easy-to-use four-pin interface
■ Low current during configuration and near-zero standby mode current
■ Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers
■ Available in compact plastic packages
■ 8-pin plastic dual in-line (PDIP) package
■ 20-pin plastic J-lead chip carrier (PLCC) package
■ 32-pin plastic thin quad flat pack (TQFP) package
■ EPC2 device has reprogrammable flash configuration memory
■ 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.
1149.1 JTAG interface
■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
■ Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable
■ Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices
■ nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration

Specifications

Attribute Attribute Value
Manufacturer Intel / Altera
Product Category FPGAs (Field Programmable Gate Array)
Series Stratix® GX
Product Stratix GX
Packaging  Tray
Mounting-Style SMD/SMT
Tradename Stratix GX
Package-Case 1020-BBGA, FCBGA
Operating-Temperature  -40°C ~ 100°C (TJ)
Mounting-Type Surface Mount
Voltage-Supply  1.425 V ~ 1.575 V
Supplier-Device-Package 1020-FBGA (33x33)
IC Number of Gates   
Number-of-I-O 607 I/O
Data-Rate  3.1875 Gbps
Number-of-LABs-CLBs 2566
Number-of-Logic-Elements-Cells  25660
Total-RAM-Bits  1944576 Bits
Maximum Operating Temperature  + 85 C
Operating temperature range - 40 C
Operating-Supply-Voltage  1.5 V to 3.3 V
Maximum-Operating-Frequency  650 MHz
Package-Case FBGA-1020
Number-of-Transceivers 16 Transceivers
Input/output  607 I/O
Number-of-Logic-Array-Blocks-LABs 2566
Number-of-Logic-Elements  25660 Logic Elements
Total-Memory 1944576 bit
 

Form,Package,Functional compatible component

Descriptions

IC FPGA 607 I/O 1020FBGA
FPGA Stratix庐 GX Family 25660 Cells 5000MHz 130nm Technology 1.5V 1020-Pin FC-FBGA
FPGA - Field Programmable Gate Array FPGA - Stratix I GX 2566 LABs 607 IOs

 

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