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EP1C3T100C6N Programmable Logic ICs FPGA - Field Programmable Gate Array FPGA - Cyclone I 291 LABs 65 IOs
  • EP1C3T100C6N Programmable Logic ICs FPGA - Field Programmable Gate Array FPGA - Cyclone I 291 LABs 65 IOs

EP1C3T100C6N Programmable Logic ICs FPGA - Field Programmable Gate Array FPGA - Cyclone I 291 LABs 65 IOs

Place of Origin Call
Brand Name Lattice Semiconductor
Certification ROHS
Model Number EP1C3T100C6N
Product Details
Product Name:
EP1C3T100C6N
Condition:
Original 100%
Installation Methodpe:
CPLD 550 MHz Surface Mount 0°C ~ 85°C (TJ) Tray MachXO 256-FTBGA (17x17)
Package:
256-LBGA
Voltage - Supply:
International Standard
Max. Reverse Current:
International Standard
Application:
CPLDs (Complex Programmable Logic Devices)
Product Description

                                                                  EP1C3T100C6N Programmable Logic ICs FPGA - Field Programmable Gate Array FPGA - Cyclone I 291 LABs 65 IOs 0LCMXO640C-4FTN256C Datasheet
Product Details

Introduction

The MachXO is optimized to meet the requirements of applications traditionally addressed by CPLDs and low capacity FPGAs: glue logic, bus bridging, bus interfacing, power-up control, and control logic. These devices bring together the best features of CPLD and FPGA devices on a single chip.

Features

■ Non-volatile, Infinitely Reconfigurable
• Instant-on – powers up in microseconds
• Single chip, no external configuration memory
required
• Excellent design security, no bit stream to
intercept
• Reconfigure SRAM based logic in milliseconds
• SRAM and non-volatile memory programmable
through JTAG port
• Supports background programming of
non-volatile memory
■ Sleep Mode
• Allows up to 100x static current reduction
■ TransFR™ Reconfiguration (TFR)
• In-field logic update while system operates
■ High I/O to Logic Density
• 256 to 2280 LUT4s
• 73 to 271 I/Os with extensive package options
• Density migration supported
• Lead free/RoHS compliant packaging
■ Embedded and Distributed Memory
• Up to 27.6 Kbits sysMEM™ Embedded Block
RAM
• Up to 7.5 Kbits distributed RAM
• Dedicated FIFO control logic
■ Flexible I/O Buffer
• Programmable sysIO™ buffer supports wide
range of interfaces:
− LVCMOS 3.3/2.5/1.8/1.5/1.2
− LVTTL
− PCI
− LVDS, Bus-LVDS, LVPECL, RSDS
■ sysCLOCK™ PLLs
• Up to two analog PLLs per device
• Clock multiply, divide, and phase shifting
■ System Level Support
• IEEE Standard 1149.1 Boundary Scan
• Onboard oscillator
• Devices operate with 3.3V, 2.5V, 1.8V or 1.2V
power supply
• IEEE 1532 compliant in-system programming
Specifications

Attribute Attribute Value
Manufacturer Lattice Semiconductor
Product Category CPLDs (Complex Programmable Logic Devices)
Series MachXO
Product MachXO
Packaging  Tray
Mounting-Style SMD/SMT
Package-Case 256-LBGA
Operating-Temperature 0°C ~ 85°C (TJ)
Mounting-Type Surface Mount
Voltage-Supply  1.71 V ~ 3.465 V
Supplier-Device-Package 256-FTBGA (17x17)
IC Number of Gates  -
Number-of-I-O 159 I/O
Number-of-LABs-CLBs 80
Number-of-Logic-Elements-Cells  640
Total-RAM-Bits -
Maximum Operating Temperature  + 85 C
Operating temperature range  0 C
Operating-Supply-Voltage  1.8 V 2.5 V 3.3 V
Operating-Supply-Current  17 mA
Maximum-Operating-Frequency  550 MHz
Package-Case FTBGA-256
Input/output  159 I/O
Number-of-Logic-Array-Blocks-LABs 80
Number-of-Logic-Elements 640 Logic Elements
Total-Memory  6.1 kbit
Distributed-RAM  6.1 kbit
 

Descriptions

IC FPGA 159 I/O 256FTBGA
CPLD MachXO Family 320 Macro Cells 1.8V/2.5V/3.3V 256-Pin FTBGA Tray
FPGA - Field Programmable Gate Array 640 LUTs 159 IO 1.8/ 2.5/3.3V -4 Spd

 
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