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EPM7256AETC144-7 CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 256 Macro 36 IOs
  • EPM7256AETC144-7 CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 256 Macro 36 IOs

EPM7256AETC144-7 CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 256 Macro 36 IOs

Place of Origin Call
Brand Name Intel / Altera
Certification ROHS
Model Number EPM7256AETC144-7
Product Details
Product Name:
EPM7256AETC144-7
Condition:
Original 100%
Installation Methodpe:
CPLDs (Complex Programmable Logic Devices)
Package:
144-LQFP
Voltage - Supply:
International Standard
Max. Reverse Current:
International Standard
Application:
CPLDs (Complex Programmable Logic Devices)
Product Description

                                                         EPM7256AETC144-7 CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 256 Macro 36 IOs 0EPM7256AETC144-7 Datasheet

Product Details

General Description

MAX 7000A (including MAX 7000AE) devices are high-density, highperformance devices based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROMbased MAX 7000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing requirements for 33 MHz operation of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.

Features...

■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1)
■ 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
– MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532
– EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532
■ Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
■ Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71
■ Enhanced ISP features
– Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices)
– ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices)
– Pull-up resistor on I/O pins during in-system programming
■ Pin-compatible with the popular 5.0-V MAX 7000S devices
■ High-density PLDs ranging from 600 to 10,000 usable gates
■ Extended temperature range
■ 4.5-ns pin-to-pin logic delays with counter frequencies of up to
227.3 MHz
■ MultiVoltTM I/O interface enables device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), spacesaving FineLine BGATM, and plastic J-lead chip carrier (PLCC) packages
■ Supports hot-socketing in MAX 7000AE devices
■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance
■ PCI-compatible
■ Bus-friendly architecture, including programmable slew-rate control
■ Open-drain output option
■ Programmable macrocell registers with individual clear, preset, clock, and clock enable controls
■ Programmable power-up states for macrocell registers in MAX 7000AE devices
■ Programmable power-saving mode for 50% or greater power reduction in each macrocell
■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell
■ Programmable security bit for protection of proprietary designs
■ 6 to 10 pin- or logic-driven output enable signals
■ Two global clock signals with optional inversion
■ Enhanced interconnect resources for improved routability
■ Fast input setup times provided by a dedicated path from I/O pin to macrocell registers
■ Programmable output slew-rate control
■ Programmable ground pins

Specifications

Attribute Attribute Value
Manufacturer Intel / Altera
Product Category CPLDs (Complex Programmable Logic Devices)
Series MAX® 7000A
Product MAX 7000A
Packaging  Tray
Unit-Weight  0.046530 oz
Mounting-Style SMD/SMT
Tradename MAX 7000
Package-Case 144-LQFP
Operating-Temperature  0°C ~ 70°C (TA)
Mounting-Type Surface Mount
Supplier-Device-Package 144-TQFP (20x20)
Memory-Type  EEPROM
Programmable-Type  In System Programmable
Delay-Time-tpd-1-Max 7.5ns
Voltage-Supply-Internal 3 V ~ 3.6 V
Number-of-Logic-Elements-Blocks  16
Number-of-Macrocells 256 Macrocells
IC Number of Gates 5000
Number-of-I-O 120 I/O
Maximum Operating Temperature  + 70 C
Operating temperature range  0 C
Operating-Supply-Voltage  3.3 V
Maximum-Operating-Frequency  172.4 MHz
Supply-Voltage-Max  3.6 V
Supply-Voltage-Min  3 V
Package-Case TQFP-144
Propagation-Delay-Max  5.5 ns
Input/output  36 I/O
Number-of-Logic-Array-Blocks-LABs 16

Form,Package,Functional compatible component

Descriptions

CPLD MAX庐 7000A Family 5K Gates 256 Macro Cells 126.6MHz 3.3V 144-Pin TQFP Tray
CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 256 Macro 36 IOs

 

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